Progress in Z²-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage

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• 作者：Jing Wan^a ; ^{jing.wan01@gmail.com} ; Cyrille Le Royer^b ; Alexander Zaslavsky^c ; Sorin Cristoloveanu^a
• 关键词：Z2-FET ; One-transistor DRAM ; Capacitor-less DRAM ; Retention ; Selective array addressing ; Dual bit storage
• 刊名：Solid-State Electronics
• 出版年：2013
• 出版时间：June, 2013
• 年：2013
• 卷：84
• 期：Complete
• 页码：147-154
• 全文大小：2643 K

文摘

In this paper, we extend our studies on the use of zero impact ionization and zero subthreshold swing field-effect-transistor (Z²-FET) as a capacitor-less one-transistor dynamic random access memory (1T-DRAM) through both experiment and TCAD simulation. The data retention time is measured as a function of biasing, temperature and device dimensions, leading to a simple predictive model. An alternative writing method using the source MOSFET is presented, which is potentially more compatible with the conventional DRAM array design. The operation of a Z²-FET memory array is discussed, in which the write and read signals are adapted from the single cell to achieve selective operation. Finally, we present simulations demonstrating that the Z²-FET can be used to store multiple bits thanks to the charges on both the top and bottom gate capacitors.