Modeling and simulation of circuits with shared structurally synthesized BDDs

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• 作者：Raimund Ubar ^{raiub@pld.ttu.ee} ; Lembit Jü ; rimä ; gi ; ^{lembit.jyrimagi@gmail.com} ; Jaan Raik ^{jaan@pld.ttu.ee} ; Vladimir Viies ^{viis@ati.ttu.ee}
• 关键词：Combinational and sequential circuits ; Logic simulation ; BDDs ; Minimization of BDDs ; SSBDDs
• 刊名：Microprocessors and Microsystems
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：48
• 期：Complete
• 页码：56-61
• 全文大小：1027 K
• 卷排序：48

文摘

Modeling and simulation are critical tools for the analysis of testability and verification of digital circuits. BDDs are a well-known model for manipulating Boolean functions. However, the traditional BDDs mainly address modeling the function of the digital circuits, and not the structural aspects that are important for testability analysis. We propose a new type of BDD in the form of Shared Structurally Synthesized BDD (S3BDD) for representing the structure and simulating the faults in digital circuits. The paper presents a method for synthesis of S3BDDs, offers a formula for calculating the minimal size of the model, and proposes a method for parallel pattern simulation with S3BDDs We demonstrate a considerable increase in the speed-up of simulation of digital circuits using S3BDDs.