Analytical modeling of the lattice and thermo-elastic coefficient mismatch-induced stress into silicon nanowires horizontally embedded on insulator-on-silicon substrates

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• 作者：Sulagna Chatterjee^a ; Sanatan Chattopadhyay^b ; ^{scelc@caluniv.ac.in}
• 关键词：Silicon-nanowire (Si-nanowire) ; Stress modeling ; Insulator-on-silicon substrate ; Electron mobility ; Hole mobility
• 刊名：Superlattices and Microstructures
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：101
• 期：Complete
• 页码：384-396
• 全文大小：1486 K
• 卷排序：101

文摘

Analytical calculation of substrate- and process-induced stress is developed for partially embedded nanowires. Induced stress is estimated for different fractional insertions and orientations of horizontal nanowires. Hole and electron mobility have been made equal by engineering fractions of insertion within the insulating layer.