A Distributed Run-Time Environment for the Kalray MPPA^?-256 Integrated Manycore Processor

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• 作者：Benoî ; t Dupont de Dinechin ; ^{benoit.dinechin@kalray.eu} ; Pierre Guironnet de Massas ; Guillaume Lager ; Clé ; ment Lé ; ger ; Benjamin Orgogozo ; Jé ; rô ; me Reybert ; Thierry Strudel
• 关键词：Distributed Memory ; POSIX IPC ; Network-on-Chip
• 刊名：Procedia Computer Science
• 出版年：2013
• 出版时间：2013
• 年：2013
• 卷：18
• 期：Complete
• 页码：1654-1663
• 全文大小：617 K

文摘

The Kalray MPPA?-256 is a single-chip manycore processor that integrates 256 user cores and 32 system cores in 28 nm CMOS technology. These cores are distributed across 16 compute clusters of 16+1 cores, and 4 quad-core I/O subsystems. Each compute cluster and I/O subsystem owns a private address space, while communication and synchronization between them is ensured by data and control Networks-on-Chip (NoC). This processor targets embedded applications whose program- ming models fall within the following classes: Kahn Process Networks (KPN), as motivated by media processing; single program multiple data (SPMD), traditionally used for numerical kernels; and time-triggered control systems.

We describe a run-time environment that supports these classes of programming models and their composition. This environment combines classic POSIX single-process multi-threaded execution inside the compute clusters and I/O subsystems, with a set of specific Inter-Process Communication (IPC) primitives that exploit the NoC architecture. We combine these primitives in order to provide the run-time support for the different target programming models. Interestingly enough, all these NoC-specific IPC primitives can be mapped to a subset of the classic synchronous and asynchronous POSIX file descriptor operations. This design thus extends the canonical ¡®pipe-and-filters¡¯ software component model, where POSIX processes are the atomic components, and IPC instances are the connectors.