CNFET-based approximate ternary adders for energy-efficient image processing applications

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• 作者：Atiyeh Panahi^aAuthor Vitae ; Fazel Sharifi^aAuthor Vitae ; Mohammad Hossein Moaiyeri^a ; ^bAuthor Vitae ; Keivan Navi^a ; ^{navi@sbu.ac.ir} ; ^{knavi@uci.edu}Author Vitae
• 关键词：Approximate computing ; CNFET ; Full adder ; Multiple valued logic (MVL)
• 刊名：Microprocessors and Microsystems
• 出版年：2016
• 出版时间：November 2016
• 年：2016
• 卷：47
• 期：part_PB
• 页码：454-465
• 全文大小：2978 K
• 卷排序：47

文摘

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.