Efficient FPGA implementation of modular multiplication based on Montgomery algorithm

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• 作者：Yatao Yang^a ; ^{yt006@sohu.com}Author Vitae ; Chao Wu^bAuthor Vitae ; Zichen Li^a ; ^cAuthor Vitae ; Junming Yang^aAuthor Vitae
• 关键词：Montgomery modular multiplication ; FPGA ; Multiplier IP cores ; Addition IP cores
• 刊名：Microprocessors and Microsystems
• 出版年：2016
• 出版时间：November 2016
• 年：2016
• 卷：47
• 期：part_PA
• 页码：209-215
• 全文大小：1446 K
• 卷排序：47

文摘

In order to improve the efficiency of modular multiplication algorithm for FPGA implementation on the prime field modular, an efficient scheme is proposed to accomplish 256 × 256 bits modular multiplication algorithm. The embedded IP cores of Xilinx FPGA are efficiently utilized to design 512-bit addition and 256 × 256 bits multiplier. Moreover, the above modules are used to complete Montgomery modular multiplication algorithm. Compared with traditional implementation method, almost 50% running efficiency is improved in our scheme, which has important value to implement complicated cryptographic processor in hardware environment.