Summarized the current 22 nm advanced semiconductor process and integration design of element processes.
Conducted hazard analysis of current 22 nm advanced semiconductor process, tools, and facility by using FMEA.
Proposed the CVD thin film deposition of TEOS (tetraethyl orthosilicate) process conditions.
Proposed the IPD process applied on the 22 nm MOSFETs, with a thickness of 5000 Å and process time of 60 min.
Reduction of power consumption satisfied the attenuation strategy of ISD and converted power output up to 3971 W.