Design of Testable Adder in Quantum‐dot Cellular Automata with Fault Secure Logic

详细信息    查看全文

• 作者：Mrinal Goswami^a ; ^{mrinal.goswami21@gmail.com} ; Bibhash Sen^a ; ^{bibhash.sen@cse.nitdgp.ac.in} ; Rijoy Mukherjee^a ; ^{rijoy.mukherjee@gmail.com} ; Biplab K Sikdar^b
• 关键词：Quantum-dot cellular automata (QCA) ; QCA defects ; Parity preserving logic ; Testability ; Nano-electronics
• 刊名：Microelectronics Journal
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：60
• 期：Complete
• 页码：1-12
• 全文大小：1860 K
• 卷排序：60

文摘

A testable parity preserving full adder (t-Adder) is designed considering its primary outputs. Reliability issue is addressed with the success of 100% fault coverage with only 3 (three) test vectors. The power dissipation of the t-Adder is analysed which ensures low power consumption. To make robust fault secure t-Adder, path fault secure (PFS) scheme (first time in QCA circuit) is riveted to it. Further, t-Adder is used to design a simple testable ALU with high logical depth.