Low latency radiation tolerant self-repair reconfigurable SRAM architecture
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- 作者：Nikolaos Eftaxiopoulos ; eftaxiopoulos@microlab.ntua.gr" class="auth_mail" title="E-mail the corresponding author ; Nicholas Axelos njaxel@microlab.ntua.gr" class="auth_mail" title="E-mail the corresponding author ; Kiamal Pekmestzi pekmes@microlab.ntua.gr" class="auth_mail" title="E-mail the corresponding author
- 关键词：Low latency ; Soft error tolerance ; Reconfiguration ; Self-repair ; Single-bit upset (SBU) ; Multi-bit upset (MBU)
- 刊名：Microelectronics Reliability
- 出版年：2016
- 出版时间：January 2016
- 年：2016
- 卷：56
- 期：Complete
- 页码：202-211
- 全文大小：2014 K
文摘
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A radiation tolerant SRAM architecture able to deal with single and multi-bit errors is proposed.
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No extra cycles for detection/correction of the error are required. The correction is performed during the read cycle.
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Operation at high frequencies is provided even in worst corner conditions. When fault-free, the induced latency is zero.
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An accelerator circuit is proposed for higher repair frequencies.
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The architecture is reconfigurable with two provided configurations (Fault Tolerance and Full Capacity).