AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

详细信息    查看全文

• 作者：Nuno Lourenç ; o ^{nlourenco@lx.it.pt" class="auth_mail" title="E-mail the corresponding author}Author Vitae ; Ricardo Martins ; ^{ricmartins@lx.it.pt" class="auth_mail" title="E-mail the corresponding author}Author Vitae ; Antó ; nio Canelas ^{acanelas@lx.it.pt" class="auth_mail" title="E-mail the corresponding author}Author Vitae ; Ricardo Pó ; voa ^{rpovoa@lx.it.pt" class="auth_mail" title="E-mail the corresponding author}Author Vitae ; Nuno Horta ^{nuno.horta@lx.it.pt" class="auth_mail" title="E-mail the corresponding author}Author Vitae
• 关键词：Analog integrated circuits ; Automatic layout generation ; Electronic design automation ; Layout-aware sizing ; Post-layout performance ; Robust design
• 刊名：Integration, the VLSI Journal
• 出版年：2016
• 出版时间：September 2016
• 年：2016
• 卷：55
• 期：Complete
• 页码：316-329
• 全文大小：5774 K

文摘

This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated for analog IC sizing and layout generation. Results are validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO® or CALIBRE®.