A new area-efficient BCD-digit multiplier

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• 作者：Encarnació ; n Castillo^a ; ^encas@ugr.esAuthor Vitae ; Antonio Lloris^aAuthor Vitae ; Diego P. Morales^aAuthor Vitae ; Luis Parrilla^aAuthor Vitae ; Antonio Garcí ; a^aAuthor Vitae ; Guillermo Botella^bAuthor Vitae
• 关键词：BCD enconding ; Computer arithmetic ; FPGA ; IoT ; Multiplier
• 刊名：Digital Signal Processing
• 出版年：2017
• 出版时间：March 2017
• 年：2017
• 卷：62
• 期：Complete
• 页码：1-10
• 全文大小：1516 K
• 卷排序：62

文摘

In the Internet of Things era, with millions of devices performing financial and commercial operations, decimal arithmetic has become very popular in the computation of many business and commercial applications, in order to maintain decimal rounding and precision. This paper proposes the design and implementation of a new algorithm for decimal multiplication oriented to area reduction. This algorithm is especially suitable for field programmable gate arrays (FPGA) and has thus been implemented on this kind of devices. Results show that the proposed BCD multiplication leads to a significant area reduction without decreasing system performance.