A 32 GBit/s communication SoC for a waferscale neuromorphic system
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- 作者：Stefan ; Scholze ; Holger ; Eisenreich ; Sebastian ; Hö ; ppner ; Georg ; Ellguth ; Stephan ; Henker ; Mario ; Ander ; Stefan ; Hä ; nzsche ; Johannes ; Partzsch ; Christian ; Mayr ; ; ; Christian.Mayr@tu-dresden.de ; René ; ; Schü ; ffny[Author vitae]
- 关键词：Gigaevent packet-based AER ; Configuration over AER ; Low-voltage-differential-signaling ; Serial data transmission ; Clock-to-data alignment
- 刊名：Integration, the VLSI Journal
- 出版年：2012
- 出版时间：January 2012
- 年：2012
- 卷：45
- 期：1
- 页码：61-75
- 全文大小：3089 K
文摘
State-of-the-art large-scale neuromorphic systems require a sophisticated, high-bandwidth communication infrastructure for the exchange of spike events between units of the neural network. These communication infrastructures are usually built around custom-designed FPGA systems. However, the overall bandwidth requirements and the integration density of very large neuromorphic systems necessitate a significantly more targeted approach, i.e. the development of dedicated integrated circuits. We present a VLSI realization of a neuromorphic communication system-on-chip (SoC) with a cumulative throughput of 32 GBit/s in CMOS, employing state-of-the-art circuit blocks. Several of these circuits exhibit improved performance compared to current literature, e.g. a priority queue with a speed of 31 Mkeys/s at 1.3 mW, or a 1 GHz PLL at 5 mW. The SoC contains additional neuromorphic functionality, such as configurable event delays and event ordering. The complete configuration of the neuromorphic system is also handled by the spike communication channels, in contrast to the separate channels required in the majority of current systems. At 865 Mevent/s, the SoC delivers at least a factor of eight more bandwidth than other current neuromorphic communication infrastructures.