UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs
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- 作者：Cinzia BernardeschiaAuthor Vitae ; Luca CassanoaAuthor Vitae ; Andrea Domenicia ; andrea.domenici@ing.unipi.it" class="auth_mail" title="E-mail the corresponding authorAuthor Vitae ; Luca SterponebAuthor Vitae
- 关键词：Single Event Upset ; SRAM-based FPGA ; Untestability analysis ; Model checking
- 刊名：Integration, the VLSI Journal
- 出版年：2016
- 出版时间：September 2016
- 年：2016
- 卷：55
- 期：Complete
- 页码：85-97
- 全文大小：1182 K
文摘
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UA2TPG supports on-line testing of the configuration memory of SRAM-based FPGAs.
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Off-line detection of untestable SEUs reduces ATPG search space.
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Only the configuration bits used by the specific application are considered.
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Model checking is used to formally prove untestability and generate test patterns.
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Results show test pattern generation with 100% coverage of testable SEU events.