Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

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• 作者：Pilin Junsangsri^a ; ^{junsangsri.p@husky.neu.edu" class="auth_mail" title="E-mail the corresponding author} ; Jie Han^b ; ^{jhan8@ualberta.ca" class="auth_mail" title="E-mail the corresponding author} ; Fabrizio Lombardi^a ; ^{lombardi@ece.neu.edu" class="auth_mail" title="E-mail the corresponding author}
• 关键词：Nonvolatile SRAM Cell ; Emerging technology ; Programmable Metallization Cell (PMC) ; Single Event Upset (SEU) ; Hybrid memory
• 刊名：Integration, the VLSI Journal
• 出版年：2016
• 出版时间：January 2016
• 年：2016
• 卷：52
• 期：Complete
• 页码：156-167
• 全文大小：1491 K

文摘

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6 T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit.