An extended dual input dual output three level Z source inverter with improved switch loss reduction technique

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• 作者：N.B. Deshmukh ; ^{nbd.nmt@gmail.com} ; R.D. Thombare ^{vrthombare@gmail.com} ; M.M. Waware ; D.S. More
• 关键词：Dual input dual output three level inverter ; Loss area ; &ldquo ; No switching zone&rdquo ; SPWM ; Z source network
• 刊名：Journal of Electrical Systems and Information Technology
• 出版年：2016
• 出版时间：December 2016
• 年：2016
• 卷：3
• 期：3
• 页码：398-410
• 全文大小：2685 K
• 卷排序：3

文摘

Multilevel inverter (MLI) is a proven technology used for industrial applications due to low output total harmonic distortion (THD), high power handling capability and low active device rating. Dual output inverter is a recent trend associated with inverter topologies for specialized applications. This paper deals with three phase three level dual input dual output inverter topology with minimum active device count. Reduction in switch count leads to reduction in losses and improves reliability. Both the input sources share power equally as neutral point current ripple is maintained low. For further reduction in switching losses at higher switching frequencies, the concept of “no switching zone” or discontinuous pulse width modulation (DPWM) has been put forth recently. This paper proposes modification in the placement of “no switching zone” in order to optimize switching losses and output THD (output filtering requirements) for low power factor load. This study also proposes novel graphical approach to analyze the loss reduction along with its effect on output THD. The sinusoidal PWM (SPWM) is used which gives satisfactory switching loss reduction without complex calculations. Moreover, the proposed topology is generalized to provide dual output at higher voltage levels. It is seen that the components reduction phenomenon becomes more pronounced as number of levels goes on increasing. The proposed converter is simulated in MATLAB software environment and results are obtained.