Enabling interconnect scaling with Spacer-Defined Double Patterning (SDDP)
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- 作者：Yong Kong Siew ; Michele Stucchi ; Janko Versluijs ; Philippe Roussel ; Eddy Kunnen ; Marianna Pantouvaki ; Gerald P. Beyer ; Zsolt Tokei
- 关键词：Spacer-Defined Double Patterning (SDDP) ; Line Edge Roughness (LER) ; Line Edge Roughness (LER) correlation ; Time-Dependent Dielectric Breakdown (TDDB)
- 刊名：Microelectronic Engineering
- 出版年：2013
- 出版时间：December, 2013
- 年：2013
- 卷：112
- 期：Complete
- 页码：116-120
- 全文大小：1903 K
文摘
Line Edge Roughness (LER) correlation improves the interconnect Time-Dependent Dielectric Breakdown (TDDB) lifetime significantly with respect to non-correlated interconnect based on simulation [M. Stucchi, P. Roussel, Z. T?kei, S. Demuynck, G. Groeseneken, IEEE Trans. Device Mater. Reliab. 99 (2011)] [1]. On the other hand, 50 % Line Edge Roughness (LER) correlation has been observed experimentally after spacer formation in 20 nm half pitch (HP) interconnects using a Spacer-Defined Double Patterning (SDDP) approach. Comparisons of breakdown field distribution and TDDB lifetime for SDDP patterned 20 nm HP and Litho-Etch-Litho-Etch (LELE) patterned 35 nm HP Cu interconnect confirm that the SDDP approach offers potential benefits for TDDB lifetime, which enable future interconnect scaling.