Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages

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• 作者：G.V. Luong^a ; ^{g.luong@fz-juelich.de" class="auth_mail" title="E-mail the corresponding author} ; S. Strangio^b ; A. Tiedemannn^a ; S. Lenk^a ; S. Trellenkamp^a ; K.K. Bourdelle^c ; Q.T. Zhao^a ; ^{q.zhao@fz-juelich.de" class="auth_mail" title="E-mail the corresponding author} ; S. Mantl^a
• 关键词：Si nanowire TFET ; Analog performance ; Gate-all-around ; Inverter ; C-TFET ; Subthreshold slope
• 刊名：Solid State Electronics
• 出版年：2016
• 出版时间：January 2016
• 年：2016
• 卷：115
• 期：part_PB
• 页码：152-159
• 全文大小：2481 K

文摘

In this work, strained Si (sSi) nanowire array of n-TFETs with gates all around (GAA) yielding ON-currents of 5 μA/μm at a supply voltage V_dd = 0.5 V are presented. Tilted ion implantation with BF₂⁺ into NiSi₂ dopant has been used to form a highly doped pocket for the source to channel tunneling junction. These devices indicate sub-threshold slopes (SS) below 60 mV/dec for I_d < 10⁻⁴ μA/μm at V_ds = 0.1 V at room temperature. Common analog device characteristics have been determined at V_dd = 0.5 V resulting in a transconductance g_m = 24 μS/μm, transconductance efficiency g_m/I_d = 23 V⁻¹ and the conductance g_d = 0.8 μS/μm normalized to the gate width. Based on the good saturation behavior in the output characteristic, an intrinsic gain of 188 is observed. In addition, we present operation of the first experimental sSi GAA NW C-TFET inverter. In spite of ambipolar behavior, the voltage transfer curves (VTC) indicate wide and constant noise margin levels with steep transitions offering a voltage gain of 25 at V_dd = 1 V.