The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

详细信息    查看全文

• 作者：G. Aglieri Rinella ; M. Fiorini ; P. Jarron ; J. Kaplon ; A. Kluge ; E. Martin ; M. Morel ; M. Noy ; L. Perktold ; K. Poltorak
• 关键词：Front-end electronics ; TDCpix ; Gigatracker ; hybrid pixels ; sub-nanosecond timing
• 刊名：Physics Procedia
• 出版年：2012
• 出版时间：2012
• 年：2012
• 卷：37
• 期：Complete
• 页码：1608-1617
• 全文大小：702 K

文摘

NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak ?ow of particles crossing the detector modules reaches 1.27 MHz/mm² fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements.

The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300¡Á300 ¦Ìm2 arranged in a matrix of 45 rows ¡Á 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99 % .

The chosen architecture provides full separation of the sensitive analog ampli?ers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the ?ne time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ¡«100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the ?nal TDCpix is given in this paper. Design choices and some technical implementation details are presented.

Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of speci?cation ?gures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in this contribution.

The ongoing R&Deffort provided an understanding of some of the processes limiting the timing resolution that can beachievedwithhybridplanarpixels.Some considerationsonthese aspectsare discussedatlast.