Proposed work uses drain and gate work function engineering on the charge plasma tunnel field effect transistor. The use of gate work function engineering by creating a section of lower work function of gate electrode near to channel/source interface provides the steeper subthreshold slope; improve ON-state current and significant reduction in threshold voltage. The drain work function engineering by creating a section of relatively higher work function near to channel region of the drain terminal which is used to induce the N+ region widens the lateral tunneling distance on the drain/channel interface to prevent the flow of holes on the same junction. This provides lower gate to drain capacitance results in better channel controlling and improved high frequency figure of merit.