Improvement to the signaling interface for CMOS pixel sensors

详细信息    查看全文

• 作者：Zhan Shi^a ; ^{sz1134@163.com" class="auth_mail" title="E-mail the corresponding author} ; Zhenan Tang^a ; ^{tangza@dlut.edu.cn" class="auth_mail" title="E-mail the corresponding author} ; Chong Feng^a ; ^b ; Hong Cai^a
• 关键词：CMOS pixel sensors (CPS) ; Particle tracking ; Interface ; High speed ; Low power consumption
• 刊名：Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
• 出版年：2016
• 出版时间：1 October 2016
• 年：2016
• 卷：832
• 期：Complete
• 页码：77-84
• 全文大小：1672 K

文摘

The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 µm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.