Speed-up of scalable iterative linear solvers implemented on an array of transputers

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• 作者：Asenov ; A. ; Reid ; D. ; Barker ; J.R.
• 关键词：Parallel iterative solvers ; Processor array ; Transputers ; Speed-up prediction
• 刊名：Parallel Computing
• 出版年：1995
• 出版时间：April, 1995
• 年：1995
• 卷：21
• 期：4
• 页码：669-682
• 全文大小：658 K

文摘

A detailed model is presented for the speed-up of parallel linear iterative solvers. The mapping of a topologically rectangular discrete grid onto a processor array of N × M transputers leads to step-like behaviour in the local communication and calculation time. This results in a typical oscillatory behaviour of ‘speed-up’ when problem sizes are increased monotonously. The theory is compared with experimental results obtained on a Parsytec Super Cluster Model 64 using a black-red SOR algorithm coded in 3L Parallel Fortran.