Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

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• 作者：Gang Chen^aAuthor Vitae ; Biao Hu^aAuthor Vitae ; Kai Huang ; ^a ; ^b ; ^{huangk36@mail.sysu.edu.cn" class="auth_mail" title="E-mail the corresponding author}Author Vitae ; Alois Knoll^aAuthor Vitae ; Kai Huang^cAuthor Vitae ; Di Liu^dAuthor Vitae ; Todor Stefanov^dAuthor Vitae ; Feng Li^bAuthor Vitae
• 关键词：Cache interference ; Dynamic cache partitioning ; Scheduling ; Real-time multi-core systems
• 刊名：Microprocessors and Microsystems
• 出版年：2016
• 出版时间：May 2016
• 年：2016
• 卷：42
• 期：Complete
• 页码：200-214
• 全文大小：3187 K

文摘

Shared cache in modern multi-core systems has been considered as one of the major factors that degrade system predictability and performance. How to manage the shared cache for real-time multi-core systems in order to optimize the system performance while guaranteeing the system predictability is an open issue. In this paper, we present a reconfigurable cache architecture which supports dynamic cache partitioning at hardware level and a framework that can exploit cache management for real-time MPSoCs. The proposed reconfigurable cache allows cores to dynamically allocate cache resource with minimal timing overhead while guaranteeing strict cache isolation among the real-time tasks. The cache management framework automatically determines time-triggered schedule and cache configuration for each task to minimize cache misses while guarantee the real-time constraints. We evaluate the proposed framework with respect to different numbers of cores and cache modules and prototype the constructed MPSoCs on FPGA. Our experiments show that, our automatic framework brings significant benefits over the state-of-the-art cache management strategies when testing 27 benchmark programs on the constructed MPSoCs.