Hardware-software collaboration for dark silicon heterogeneous many-core systems

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• 作者：Lei Yang ^{leiyang@cqu.edu.cn}Author Vitae ; Weichen Liu ; ^{wliu@cqu.edu.cn}Author Vitae ; Weiwen Jiang ^{jiang.wwen@cqu.edu.cn}Author Vitae ; Chao Chen ^{cschaochen@cqu.edu.cn}Author Vitae ; Mengquan Li ^{mengquan@cqu.edu.cn}Author Vitae ; Peng Chen ^{pengchen@cqu.edu.cn}Author Vitae ; Edwin H.M. Sha ^{edwinsha@cqu.edu.cn}Author Vitae
• 关键词：Dark silicon ; Heterogeneous many-core systems ; Big.LITTLE architecture ; Peak temperature ; Energy efficiency
• 刊名：Future Generation Computer Systems
• 出版年：2017
• 出版时间：March 2017
• 年：2017
• 卷：68
• 期：Complete
• 页码：234-247
• 全文大小：2970 K
• 卷排序：68

文摘

In dark silicon many-core systems, system-level techniques have been developed to selectively activate nonadjacent cores in physical locations to maintain the allowable power budget and eliminate thermal hotspot. However, this will unexpectedly increase communication overhead due to the longer average distance between active cores in a typical mesh-based Network-on-Chip (NoC), and in turn reduce application performance. Inspired by ARM’s big.LITTLE architecture coupled with Heterogeneous Multi-Processing (HMP) which enables energy-efficient solutions, in this paper, we propose two alternative hardware–software collaborated techniques to address the temperature/communication conflict in the dark silicon era. A Folded Torus-like NoC, FoToNoC, is presented to address the Cluster-switching based heterogeneous system, and a Quad-core-group based NoC, QcNoC, is presented to address the In-kernel switcher based heterogeneous system. Matched management strategies are accordingly proposed to collaboratively solve the trade-offs on inter-core communication, application performance, chip temperature, and system energy-efficiency in different design phases and aspects. Experimental results show that, FoToNoC   can improve as large as 36.85%36.85% on application performance, save up to 30.35%30.35% on system energy consumption and reduce chip peak temperature by 4.11∘4.11∘C on average compared with traditional techniques. Furthermore, due to the heterogeneous core organization and the fine-grained optimization on energy-efficiency in QcNoC  , averagely 18.40%18.40% reduction on system energy consumption can be achieved with an average 2.24∘2.24∘C reduction on chip peak temperature compared with that in FoToNoC  . We further demonstrate the practicality and the effectiveness of the proposed methods by case studies on real-world applications including the industry standard H.264264 decoder and DSP-stone benchmarks.