Improved SVPWM vector selection approaches in OVM region to reduce common-mode voltage for three-level neutral point clamped inverter
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- 作者：C. Bharatirajaa ; c ; bharatiraja@gmail.com" class="auth_mail" title="E-mail the corresponding author ; S. Jeevananthanb ; jeeva_9443493599@yahoo.co.in" class="auth_mail" title="E-mail the corresponding author ; J.L. Mundac ; mundajl@tut.ac.za" class="auth_mail" title="E-mail the corresponding author ; R. Lathad ; latha201180@gmail.com" class="auth_mail" title="E-mail the corresponding author
- 关键词：Common-mode voltage ; Multilevel inverter ; Diode clamped multilevel inverter ; Space vector PWM
- 刊名：International Journal of Electrical Power & Energy Systems
- 出版年：2016
- 出版时间：July 2016
- 年：2016
- 卷：79
- 期：Complete
- 页码：285-297
- 全文大小：4860 K
文摘
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An improved Analytical SVPWM model to reducing CMV developed in this paper.
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1st, the partial elimination of CMV with more voltage gain is achieved.
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2nd, full elimination of CMV with more voltage gain with zero CMV is achieved.
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The Proposed algorithms does not require any additional calculations to operate the inverter in the OVM.
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The FPGA based hardware corroboration have shown the superiority of the proposed technique over the existing SVPWM schemes.