Complete hardware evolution based SoPC for evolvable hardware

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• 作者：A. Swarnalatha^a ; ^{swarnalatha7@gmail.com" class="auth_mail} ; A.P. Shanthi^b ; ^{shanthiap@gmail.com" class="auth_mail} ; ^{apshanthi@annauniv.edu" class="auth_mail}
• 关键词：Genetic algorithm ; Evolvable hardware ; Complete hardware evolution ; FPGA ; SoPC
• 刊名：Applied Soft Computing Journal
• 出版年：May, 2014
• 年：2014
• 卷：18
• 期：Complete
• 页码：314-322
• 全文大小：940 K

文摘

Evolvable hardware (EH) is a thriving area of research which uses the genetic algorithm (GA) to construct novel circuits without manual engineering. These algorithms have been widely implemented using software but have not gained an appreciable edge because of the huge computation time involved. This has been a major hindrance to real-time applications. A major speed-up could be achieved by shifting the implementation to hardware. Major issues to be addressed in hardware implementation are scalability, providing flexibility and reduced computational delays. Presented here is the first complete hardware evolution (CHE) based system on programmable chip (SoPC) for EH. The architecture includes the required memory and modules for performing all operations of the algorithm. It is completely built on the configurable logic blocks (CLB) of a single commercial off the shelf (COTS) field programmable gate array (FPGA). The coding is done using Verilog hardware description language (HDL). Xilinx ISE 9.1i has been used for synthesis and simulation. As a proof of concept, the architecture has been synthesized for evolving three combinational circuits. The results show that the architecture is able to cater to evolution with no limit on the number of generations, accompanied with no scaling in the resource utilization. The results present computational delays of the order of a few nanoseconds for this CHE based architecture.