Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET
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- 作者：Aniruddh Sharmaa ; aniruddh.sharma07@gmail.com" class="auth_mail" title="E-mail the corresponding author ; Arushi Jaina ; arushijain1602@gmail.com" class="auth_mail" title="E-mail the corresponding author ; Yogesh Pratapb ; c ; yogi.pratap87@gmail.com" class="auth_mail" title="E-mail the corresponding author ; R.S. Guptaa ; rsgupta1943@gmail.com" class="auth_mail" title="E-mail the corresponding author
- 关键词：Junctionless transistor (JLT) ; Vacuum dielectric ; High-k dielectric ; Gate stack ; Cylindrical surrounding gate (CSG)
- 刊名：Solid State Electronics
- 出版年：2016
- 出版时间：September 2016
- 年：2016
- 卷：123
- 期：Complete
- 页码：26-32
- 全文大小：1778 K
文摘
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Asymmetric gate dielectric is proposed to enhance the hot carrier reliability.
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Full-Range drain current model is presented for vacuum oxide based junctionless transistor.
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Superposition technique has been used in this analysis.
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The design will be helpful for high reliable circuit application.