Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer

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• 作者：Shengdong Hu^a ; ^b ; ^{hushengdong@hotmail.com" class="auth_mail" title="E-mail the corresponding author} ; Jun Luo^b ; YuYu Jiang^a ; Kun Cheng^a ; Yinhui Chen^a ; Jingjing Jin^a ; Jian&rsquo ; an Wang^b ; Jianlin Zhou^a ; Fang Tang^a ; Xichuan Zhou^a ; Ping Gan^a
• 关键词：SOI LDMOS ; Breakdown voltage ; Self-heating effect ; Specific on-resistance ; Compound buried layer
• 刊名：Solid State Electronics
• 出版年：2016
• 出版时间：March 2016
• 年：2016
• 卷：117
• 期：Complete
• 页码：146-151
• 全文大小：2636 K

文摘

A novel SOI LDMOS with a partial compound buried layer structure (P-CBL SOI) is proposed in this paper. The buried oxide layer at the source-side is replaced by a compound buried layer (CBL) of “top oxide-middle polysilicon-bottom oxide”, and the buried oxide layer at the drain-side is just as the conventional SOI LDMOS (C-SOI). Firstly, a new peak of electric field is introduced at the interface and the whole lateral electric field in the top silicon layer is modulated, resulting in a higher lateral BV. Secondly, impurity doping meeting the RESURF effect in the top silicon layer is higher because the top oxide is thinner than the conventional buried oxide layer, leading to a lower R_on,sp at the on-state and an enhanced vertical BV at the off-state. Finally, thermal conductivity of polysilicon is higher than that of SiO₂, offering a lower self-heating effect. The influences of structure parameters on the devices performances are investigated. Compared with those of C-SOI LDMOS on the same top silicon layer of 4 μm, buried dielectric layer of 4 μm, and drift region of 40 μm, BV of P-CBL SOI LDMOS is enhanced by 33.4%, R_on,sp is reduced by 37.4%, and the maximum temperature at the power of 1 mW/μm is depressed by 13.3 K, respectively.