Evaluation of the ruggedness of power DMOS transistor from electro-thermal simulation of UIS behaviour
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- 作者：Daniel Donoval ; Andrej Vrbicky ; Juraj Marek ; Ales Chvala ; Peter Beno
- 关键词：Semiconductor-device characterization ; design ; and modelling ; Power VDMOS ; UIS test ; Device ruggedness ; Electro-thermal effects ; Avalanche breakdown regime ; Continual determination of maximum device temperature
- 刊名：Solid-State Electronics
- 出版年：2008
- 出版时间：June 2008
- 年：2008
- 卷：52
- 期：6
- 页码：892-898
- 全文大小：663 K
文摘
High-voltage power MOSFETs have been widely used in switching mode power supply circuits as output drivers for industrial and automotive electronic control systems. However, as the device size is reduced, the energy handling capability is becoming a very important issue to be addressed together with the trade-off between the series on-resistance RON and breakdown voltage VBR. Unclamped inductive switching (UIS) condition represents the circuit switching operation for evaluating the “ruggedness”, which characterizes the device capability to handle high avalanche currents during the applied stress. In this paper we present an experimental method which modifies the standard UIS test and allows extraction of the maximum device temperature after the applied standard stress pulse vanishes. Corresponding analysis and non-destructive prediction of the ruggedness of power DMOSFETs devices supported by advanced 2-D mixed mode electro-thermal device and circuit simulation under UIS conditions using calibrated physical models is provided also. The results of numerical simulation are in a very good correlation with experimental characteristics and contribute to their physical interpretation by identification of the mechanism of heat generation and heat source location and continuous temperature extraction.