Low-voltage low-power bulk-driven analog median filter

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• 作者：Fabian Khateb^a ; ^b ; ^{khateb@feec.vutbr.cz" class="auth_mail" title="E-mail the corresponding author} ; Montree Kumngern^c ; ^{kkmontre@kmitl.ac.th" class="auth_mail" title="E-mail the corresponding author} ; Salma Bay Abo Dabbous^a ; ^{xbayab00@stud.feec.vutbr.cz" class="auth_mail" title="E-mail the corresponding author} ; Tomasz Kulej^d ; ^{kulej@el.pcz.czest.pl" class="auth_mail" title="E-mail the corresponding author}
• 关键词：Bulk-driven MOS ; Loser-take-all ; Median filter ; Winner-take-all
• 刊名：AEU - International Journal of Electronics and Communications
• 出版年：2016
• 出版时间：May 2016
• 年：2016
• 卷：70
• 期：5
• 页码：698-706
• 全文大小：4039 K

文摘

This paper presents low-voltage (LV) low-power (LP) voltage-mode analog median filter based on winner-take-all (WTA) and loser-take-all (LTA) circuits. The LTA and WTA CMOS structures are performed utilizing bulk-driven (BD) MOS transistor (MOST) technique, enabling circuits to operate under low supply voltage of only ±0.25 V and consume extremely low-power in micro range. In addition to the simple topology of the proposed circuits, they provide high accuracy. Moreover, the common mode voltage range is near rail-to-rail. Eventually, to verify the functionality of the proposed circuits, the simulation results are carried out in Cadence environment using triple-well 0.18 μm CMOS process.