Evaluation of stereo correspondence algorithms and their implementation on FPGA

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• 作者：Carlos Colodro-Conde ; F. Javier Toledo-Moreo ; Rafael Toledo-Moreo ; J. Javier Mart铆nez-脕lvarez ; Javier Garrig贸s Guerrero ; J. Manuel Ferr谩ndez-Vicente
• 关键词：Stereo vision ; FPGA ; Embedded and real-time systems
• 刊名：Journal of Systems Architecture
• 出版年：January, 2014
• 年：2014
• 卷：60
• 期：1
• 页码：22-31
• 全文大小：3089 K

文摘

The accuracy of stereo vision has been considerably improved in the last decade, but real-time stereo matching is still a challenge for embedded systems where the limited resources do not permit fast operation of sophisticated approaches. This work presents an evaluation of area-based algorithms used for calculating distance in stereoscopic vision systems, their hardware architectures for implementation on FPGA and the cost of their accuracies in terms of FPGA hardware resources. The results show the trade-off between the quality of such maps and the hardware resources which each solution demands, so they serve as a guide for implementing stereo correspondence algorithms in real-time processing systems.