文摘
A new design approach for a three-step modified signed-digit (MSD) adder is presented that can be optically implemented using binary logic gates. The proposed scheme depends on encoding each MSD digits into a pair of binary digits using a two-state and multi-position encoding scheme. The proposed design algorithm depends on constructing the addition truth table of binary-coded MSD numbers and then using Karnaugh map to achieve output minimization. The optical binary logic gates are obtained by simply programming the decoding masks of a shadow-casting-based optical logic gate system. The proposed scheme results in a simple, compact, and efficient optical binary gate-based parallel addition system.