The dark count noise mechanisms of DSM CMOS SPADs are investigated. A field dependence of DCR model including SRH, TAT and BTBT mechanisms is derived. Each DCR component is calculated using key model parameters from TCAD simulation. The TAT tunneling is the main DCR source for SPAD devices in DSM CMOS technologies. The BTBT tunneling will be the dominant origin of DCR for the scaled DSM CMOS SPADs.