Hardware implementation of a novel water marking algorithm based on phase congruency and singular value decomposition technique

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• 作者：Manas Ranjan Nayak ; Joyashree Bag ; Souvik Sarkar ; Subir Kumar Sarkar
• 关键词：Phase congruency ; Image watermarking ; Singular value decomposition ; Matlab ; VLSI ; FPGA
• 刊名：AEU - International Journal of Electronics and Communications
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：71
• 期：Complete
• 页码：1-8
• 全文大小：2581 K
• 卷排序：71

文摘

The effortless accessibility of digital information and the simplicity of the digital systems have left the contents over the digital media extremely insecure. Digital watermark based information hiding is a prospective means for copyright protection, authentication, integrity verification and intellectual property right protection. Phase congruency technique works on the principle that perceptually significant image features have effect at spatial locations, where the essential Fourier components are maximally in phase with one another. An adaptive digital watermarking algorithm for better performance in multi-parametric solution space is developed here for hiding the copyright information by means of phase congruency and singular value decomposition supported information hiding technique. Performance evaluation of the algorithm is performed using simulation in Matlab in terms of Peak Signal to Noise Ratio, Structural Similarity Index Metrics, and Normalized Cross correlation index. Hardware realization up to the register transfer logic schematic level has been performed using high performance field programmable gate array board. The device utilization is 26% only, the dynamic power consumption of the circuit is 5.029 mW and delay after clock is 1.539 ns only. The experimental analysis establishes better robustness of the proposed algorithm as it stands against various attacks along with better data hiding capacity.