A low-area full-division-range programmable frequency divider with a 50 % duty-cycle output

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• 作者：Yu-Lung Lo ; ^{yllo@nknu.edu.tw} ; Jhih-Wei Tsai ^{d9774037@stu97.nknu.edu.tw}
• 关键词：Duty cycle ; Full-range division ; Programmable frequency divider
• 刊名：Microelectronics Journal
• 出版年：2013
• 出版时间：February, 2013
• 年：2013
• 卷：44
• 期：2
• 页码：169-175
• 全文大小：1474 K

文摘

This work presents a full-division-range programmable frequency divider with 50 % duty-cycle output. The proposed programmable frequency divider includes a programmable counter (PC) and duty-cycle-improved circuit (DCIC) to achieve full-division-range, low-area, and close-to-50 % duty-cycle output from an input clock with an arbitrary duty cycle. A chip was fabricated using 0.18-¦Ìm standard CMOS process with a 1.8-V power supply. The experimental results show that the proposed programmable frequency divider can operate correctly when input clock frequency ranges from 1 MHz to 1 GHz and division ratio ranges from 1 to 63. For an input divisor of 20 with input clock frequencies of 700 and 1 MHz and duty cycles of 20 % and 99.5 % , the output duty cycles were 50.4 % and 50 % , respectively. The total power consumption of the proposed programmable frequency divider was only 0.62 mW at 700 MHz, and the active die area was only 0.125¡Á0.05 mm².