Reducing Contact Resistance in Graphene Devices through Contact Area Patterning
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文摘
Performance of graphene electronics is limited by contact resistance associated with the metal鈥揼raphene (M鈥揋) interface, where unique transport challenges arise as carriers are injected from a 3D metal into a 2D-graphene sheet. In this work, enhanced carrier injection is experimentally achieved in graphene devices by forming cuts in the graphene within the contact regions. These cuts are oriented normal to the channel and facilitate bonding between the contact metal and carbon atoms at the graphene cut edges, reproducibly maximizing 鈥渆dge-contacted鈥?injection. Despite the reduction in M鈥揋 contact area caused by these cuts, we find that a 32% reduction in contact resistance results in Cu-contacted, two-terminal devices, while a 22% reduction is achieved for top-gated graphene transistors with Pd contacts as compared to conventionally fabricated devices. The crucial role of contact annealing to facilitate this improvement is also elucidated. This simple approach provides a reliable and reproducible means of lowering contact resistance in graphene devices to bolster performance. Importantly, this enhancement requires no additional processing steps.

Keywords:

graphene transistor; contact; resistance; contact patterning

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