High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth
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nk rel="stylesheet" type="text/css" href="/templates/jsp/css/jquery-ui-1.10.2/base/jquery-ui.min.css"/> High-Speed Pla<font color="red">n</font>ar GaAs Na<font color="red">n</font>owire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth - Na<font color="red">n</font>o Letters (ACS Publicatio<font color="red">n</font>s) http-equiv="Content-Type" content="text/html; charset=UTF-8" /> http-equiv="Content-Style-Type" content="text/css"/> http-equiv="imagetoolbar" content="no"/> name="robots" content="noarchive,nofollow" />nk rel="schema.DC" href="http://purl.org/DC/elements/1.0/" />name="dc.Title" content="High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth" />name="dc.Creator" content="Xin Miao" />name="dc.Creator" content="Kelson Chabak" />name="dc.Creator" content="Chen Zhang" />name="dc.Creator" content="Parsian K. Mohseni" />name="dc.Creator" content="Dennis Walker, Jr." />name="dc.Creator" content="Xiuling Li" />name="dc.Subject" content="Bottom-up; VLS; nanowire; III鈭扸; transistor; VLSI" />name="dc.Description" content="Wafer-scale defect-free planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics." />name="dc.Description" content="" />name="dc.Publisher" content="American Chemical Society" />name="dc.Date" scheme="WTN8601" content="December 22, 2014" />name="dc.Type" content="rapid-communication" />name="dc.Format" content="text/HTML" />name="dc.Identifier" scheme="doi" content="10.1021/nl503596j" />name="dc.Language" content="EN" />name="dc.Coverage" content="world" />name="keywords" content="Bottom-up, VLS, nanowire, III鈭扸, transistor, VLSI" />name="MSSmartTagsPreventParsing" content="true"/>nk rel="meta" type="application/atom+xml" href="http://dx.doi.org/10.1021%2Fnl503596j"/>nk rel="meta" type="application/rdf+json" href="http://dx.doi.org/10.1021%2Fnl503596j"/>nk rel="meta" type="application/unixref+xml" href="http://dx.doi.org/10.1021%2Fnl503596j"/> nk href="/templates/jsp/style.css" rel="stylesheet" type="text/css" />nk href="/templates/jsp/_style2/style.css" rel="stylesheet" type="text/css" /> nk rel="SHORTCUT ICON" href="/templates/jsp/_style2/_achs/favicon.ico" /> nk rel="stylesheet" type="text/css" media="print" href="/templates/jsp/_style2/_achs/css/atypon-print.css" /> ntent='121948137886736' property='fb:app_id' />nk href='/sda/503760/acs-main.min.css?20140529=01' rel='stylesheet' type='text/css' /> nal article pod"> n/clickThrough?id=2896080&url=http%3A%2F%2Facsmediakit.org&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264" style="text-decoration: none; border: none;"> <noscript> n/clickThrough?id=2896080&url=http%3A%2F%2Fad.doubleclick.net%2FN8868%2Fjump%2Fpubs%2Fhomepage%3Bsz%3D970x90%3Bord%3D123456789%3F&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264" target="_blank"> noscript> v> https://pubs.acs.org/action/showLogin?uri=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j" onclick="pubsLogin();return false;" id="loginButton">Log In Register n/clickThrough?id=317640&url=%2Faction%2FshowPublications%3Fdisplay%3Djournals&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264" id="journalList"> ACS Journals | n/clickThrough?id=317640&url=http%3A%2F%2Fwww.acschemworx.org&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264">ACS ChemWorx | n/clickThrough?id=317640&url=%2Fpage%2Fbooks%2Findex.html&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264">ACS eBooks | n/clickThrough?id=317640&url=%2Fisbn%2F9780841239999&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264">ACS Style Guide | n/clickThrough?id=317640&url=%2Fjournal%2Fcenear&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264">C&EN Archives | n/clickThrough?id=317640&url=%2Fpage%2Fsubscribe.html&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264">Subscribe | n/clickThrough?id=317640&url=https%3A%2F%2Fservices.acs.org%2Fpubshelp%2Fpassthru.cgi&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264" target="_blank" class="help">Help name="top" id="top"> ns Home"> vanced Search" href="/search/advanced" id="qsAdvanced">Advanced Search
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Letter

High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth

Xin Miaon class="NLM_x"> n>n class="NLM_xref-aff">鈥?/sup>n>notes-1">n class="NLM_x">ns:mml="http://www.w3.org/1998/Math/MathML" xmlns:ACS="http://namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, n>Kelson Chabakn class="NLM_x"> n>n class="NLM_xref-aff">鈥?/sup>n>n class="NLM_xref-aff">鈥?/sup>n>notes-1">n class="NLM_x">ns:mml="http://www.w3.org/1998/Math/MathML" xmlns:ACS="http://namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, n>Chen Zhangn class="NLM_x"> n>n class="NLM_xref-aff">鈥?/sup>n>n class="NLM_x">ns:mml="http://www.w3.org/1998/Math/MathML" xmlns:ACS="http://namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, n>Parsian K. Mohsenin class="NLM_x"> n>n class="NLM_xref-aff">鈥?/sup>n>n class="NLM_x">ns:mml="http://www.w3.org/1998/Math/MathML" xmlns:ACS="http://namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, n>Dennis Walkern class="NLM_x"> n>n class="NLM_x">ns:mml="http://www.w3.org/1998/Math/MathML" xmlns:ACS="http://namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, n>Jr.n class="NLM_xref-aff">鈥?/sup>n>n class="NLM_x">ns:mml="http://www.w3.org/1998/Math/MathML" xmlns:ACS="http://namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, and n>Xiuling Lin class="NLM_x"> n>*n class="NLM_xref-aff">鈥?/sup>n>n class="NLM_x"> n>鈥?/sup> Microand Nanotechnology Laboratory, n class="institution">Universityof Illinois Urbana鈭扖hampaignn>, 208 N. Wright Street, Urbana, Illinois 61801, n class="country">UnitedStatesn>鈥?/sup> n class="institution">AirForce Research Laboratory, Sensors Directoraten>, 2241 Avionics Circle, Wright-PattersonAir Force Base, Ohio 45433, n class="country">United Statesn>Nano Lett., n class="citation_year">2015n>, n class="citation_volume">15n> (5), pp 2780&ndash;2786ng>DOI: ng>10.1021/nl503596jPublication Date (Web): December 10, 2014Copyright 漏 2014 American Chemical Society*E-mail: ng@illinois.edu">xiuling@illinois.edu.

Abstract

Wafer-scale defect-free planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics.

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