Selective-Area Growth of InAs Nanowires on Ge and Vertical Transistor Application

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• 作者：Katsuhiro Tomioka ; Fumiya Izhizaka ; Takashi Fukui
• 刊名：Nano Letters
• 出版年：2015
• 出版时间：November 11, 2015
• 年：2015
• 卷：15
• 期：11
• 页码：7253-7257
• 全文大小：390K
• ISSN：1530-6992

文摘

III鈥揤 compound semiconductor and Ge are promising channel materials for future low-power and high-performance integrated circuits. A heterogeneous integration of these materials on the same platform, however, raises serious problem owing to a huge mismatch of carrier mobility. We proposed direct integration of perfectly vertically aligned InAs nanowires on Ge as a method for new alternative integrated circuits and demonstrated a high-performance InAs nanowire-vertical surrounding-gate transistor. Virtually 100% yield of vertically aligned InAs nanowires was achieved by controlling the initial surface of Ge and high-quality InAs nanowires were obtained regardless of lattice mismatch (6.7%). The transistor performance showed significantly higher conductivity with good gate control compared to Si-based conventional field-effect transistors: the drain current was 0.65 mA/渭m, and the transconductance was 2.2 mS/渭m at drain-source voltage of 0.50 V. These demonstrations are a first step for building alternative integrated circuits using vertical III鈥揤/multigate planar Ge FETs.