Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates

详细信息    查看全文

• 作者：Liangliang Zhang ; Yuzheng Guo ; Vinayak Vishwanath Hassan ; Kechao Tang ; Majeed A. Foad ; Joseph C. Woicik ; Piero Pianetta ; John Robertson ; Paul C. McIntyre
• 刊名：ACS Applied Materials & Interfaces
• 出版年：2016
• 出版时间：July 27, 2016
• 年：2016
• 卷：8
• 期：29
• 页码：19110-19118
• 全文大小：706K
• 年卷期：0
• ISSN：1944-8252

文摘

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al₂O₃/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiO_x/GeO_x surface layers, where the GeO_x-rich layer is beneath a SiO_x-rich surface. Silicon oxide regrows on the SiGe surface during Al₂O₃ atomic layer deposition, and both SiO_x and GeO_x regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiO_x–GeO_x interface layer causes large interface trap densities (D_it) due to distorted Ge–O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiO_x/GeO_x, in a selective fashion, leaving an ultrathin SiO_x interfacial layer that exhibits dramatically reduced D_it.