High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth

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作者：Xin Miao ; Kelson Chabak ; Chen Zhang ; Parsian K. Mohseni ; Dennis Walker ; Jr. ; Xiuling Li
刊名：Nano Letters
出版年：2015
出版时间：May 13, 2015
年：2015
卷：15
期：5
页码：2780-2786
全文大小：409K
ISSN：1530-6992

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et" type="text/css" href="/templates/jsp/css/jquery-ui-1.10.2/base/jquery-ui.min.css"/> High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth - Nano L<font color="red">et</font>ters (ACS Publications) eta http-equiv="Content-Type" content="text/html; charset=UTF-8" /> eta http-equiv="Content-Style-Type" content="text/css"/> eta http-equiv="imagetoolbar" content="no"/> eta name="robots" content="noarchive,nofollow" />eta name="dc.Title" content="High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth" />eta name="dc.Creator" content="Xin Miao" />eta name="dc.Creator" content="Kelson Chabak" />eta name="dc.Creator" content="Chen Zhang" />eta name="dc.Creator" content="Parsian K. Mohseni" />eta name="dc.Creator" content="Dennis Walker, Jr." />eta name="dc.Creator" content="Xiuling Li" />eta name="dc.Subject" content="Bottom-up; VLS; nanowire; III鈭扸; transistor; VLSI" />eta name="dc.Description" content="Wafer-scale defect-free planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics." />eta name="dc.Description" content="" />eta name="dc.Publisher" content="American Chemical Society" />eta name="dc.Date" scheme="WTN8601" content="December 22, 2014" />eta name="dc.Type" content="rapid-communication" />eta name="dc.Format" content="text/HTML" />eta name="dc.Identifier" scheme="doi" content="10.1021/nl503596j" />eta name="dc.Language" content="EN" />eta name="dc.Coverage" content="world" />eta name="keywords" content="Bottom-up, VLS, nanowire, III鈭扸, transistor, VLSI" />eta name="MSSmartTagsPreventParsing" content="true"/>eta" type="application/atom+xml" href="http://dx.doi.org/10.1021%2Fnl503596j"/>eta" type="application/rdf+json" href="http://dx.doi.org/10.1021%2Fnl503596j"/>eta" type="application/unixref+xml" href="http://dx.doi.org/10.1021%2Fnl503596j"/> et" type="text/css" />et" type="text/css" /> et" type="text/css" media="print" href="/templates/jsp/_style2/_achs/css/atypon-print.css" /> eta content='121948137886736' property='fb:app_id' />