High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth
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rel="stylesheet" type="text/css" href="/templates/jsp/css/jquery-ui-1.10.2/base/jquery-ui.min.css"/> High-Speed Planar GaAs Nanowi<font color="red">re</font> Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth - Nano Letters (ACS Publications) rel="schema.DC" href="http://purl.org/DC/elements/1.0/" />re Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth" />reator" content="Xin Miao" />reator" content="Kelson Chabak" />reator" content="Chen Zhang" />reator" content="Parsian K. Mohseni" />reator" content="Dennis Walker, Jr." />reator" content="Xiuling Li" />re; III鈭扸; transistor; VLSI" />ree planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics." />re, III鈭扸, transistor, VLSI" />reventParsing" content="true"/>rel="meta" type="application/atom+xml" href="http://dx.doi.org/10.1021%2Fnl503596j"/>rel="meta" type="application/rdf+json" href="http://dx.doi.org/10.1021%2Fnl503596j"/>rel="meta" type="application/unixref+xml" href="http://dx.doi.org/10.1021%2Fnl503596j"/> ref="/templates/jsp/style.css" rel="stylesheet" type="text/css" />ref="/templates/jsp/_style2/style.css" rel="stylesheet" type="text/css" /> rel="SHORTCUT ICON" href="/templates/jsp/_style2/_achs/favicon.ico" /> rel="stylesheet" type="text/css" media="print" href="/templates/jsp/_style2/_achs/css/atypon-print.css" /> ref='/sda/503760/acs-main.min.css?20140529=01' rel='stylesheet' type='text/css' /> ref="/action/clickThrough?id=2896080&url=http%3A%2F%2Facsmediakit.org&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264" style="text-decoration: none; border: none;">
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Letter

High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth

Xin Miao ref-aff">鈥?/sup>ref" href="#notes-1">reserve">, Kelson Chabak ref-aff">鈥?/sup>ref-aff">鈥?/sup>ref" href="#notes-1">reserve">, Chen Zhang ref-aff">鈥?/sup>reserve">, Parsian K. Mohseni ref-aff">鈥?/sup>reserve">, Dennis Walker reserve">, Jr.ref-aff">鈥?/sup>reserve">, and Xiuling Li ref" href="#cor1">*ref-aff">鈥?/sup> 鈥?/sup> Microand Nanotechnology Laboratory, Universityof Illinois Urbana鈭扖hampaign, 208 N. Wright Street, Urbana, Illinois 61801, UnitedStates鈥?/sup> AirForce Research Laboratory, Sensors Directorate, 2241 Avionics Circle, Wright-PattersonAir Force Base, Ohio 45433, United StatesNano Lett., 2015, 15 (5), pp 2780&ndash;2786DOI: 10.1021/nl503596jPublication Date (Web): December 10, 2014Copyright 漏 2014 American Chemical Society*E-mail: ref="mailto:xiuling@illinois.edu">xiuling@illinois.edu.

Abstract

Wafer-scale defect-free planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics.

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