文摘
Integrating high electron mobility III鈥揤 materials on an existing Si based CMOS processing platform is considered as a main stepping stone to increase the CMOS performance and continue the scaling trend. Owing to the polar nature of III鈥揤 materials versus the nonpolar nature of Si, antiphase boundaries (APBs) arise in epitaxially grown III鈥揤 materials on Si. Here, we demonstrate an approach to restrict the generation of APBs by selectively depositing a III鈥揤 material in narrow Si-trenches as formed within the shallow trench isolation (STI) patterned Si(001) wafers. Based on the detailed crystal structures of Si and III鈥揤 materials, a concept has been developed comprising the deposition in 鈥渧-grooves鈥?with {111} facets in the Si wafer. The grooves are formed by anisotropic wet etching of Si. When InP is deposited selectively into these 鈥渧-grooves鈥? the crystallographic alignment between the Si and InP restricts the APBs nucleation to the corners of the 鈥渧-grooved鈥?trench. This approach offers a promising method of large-scale integration of III鈥揤 materials on Si as required for the fabrication of novel logic and photonic devices.