Synchronous Communication-Based Many-Core SoC

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• 作者：Mouna Baklouti ; Hana Krichene ; Mohamed Abid
• 关键词：Many ; core system ; on ; chip ; Field ; programmable gate array (FPGA) ; Execution mode ; MIMD ; Synchronous communication
• 刊名：Arabian Journal for Science and Engineering
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：42
• 期：2
• 页码：845-857
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Engineering, general; Science, Humanities and Social Sciences, multidisciplinary;
• 出版者：Springer Berlin Heidelberg
• ISSN：2191-4281
• 卷排序：42

文摘

The major trend in embedded SoC (system-on-chip) design goes to fabricating chips with multiple cores operating at lower frequencies MPSoCs (multiprocessor systems on single chips) to satisfy the ever-increasing computing demands, supported by the consistently increasing number of transistors in SoCs. The number of integrated cores is more and more increasing reaching hundreds in a single chip. Such systems are called many-core embedded systems. They integrate a pool of parallel processing elements and can be added as programmable accelerators to the CPU leading to a higher performance with a low power compared to GPUs (graphical processing units). In fact, GPUs are designed for a power budget orders of magnitude higher than CPUs, making them not suitable for the embedded applications field. This paper presents a parametric many-core embedded system that can handle synchronous regular communications. The proposed high-performance architecture can run in asynchronous computing mode while assuring synchronous communications to enhance the efficiency of the routing mechanism and achieve the best possible speed-up for a wide range of data-parallel applications. This paper presents an evaluation of main used parallel execution modes and demonstrates the performance of the proposed computation model compared to others in terms of execution time. The proposed FPGA-based many-core hardware architecture performance is evaluated by various data-parallel synthetic and application benchmarks including odd-even sorting and 2D image edge detection. Experimental results show that the proposed execution mode scheduling for 2D image filtering algorithm can result in speed-up of about 20% compared to a pure asynchronous implementation.