A new CMOS comparator robust to process and temperature variations for SAR ADC converters

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• 作者：Gisela de La Fuente-Cortes…
• 关键词：Analog comparator ; ADC SAR ; Process and temperature variations ; Robust design
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：90
• 期：2
• 页码：301-308
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing;
• 出版者：Springer US
• ISSN：1573-1979
• 卷排序：90

文摘

This paper presents a novel comparator being robust to temperature and process variations. The new comparator is confronted to a conventional topology used in most of the Successive Approximations Analog to Digital Converters (SAR ADCs) for biomedical applications. To verify the benefits of the new comparator, it was designed on a CMOS 65 nm process and characterized with post layout simulations under conditions of process and temperature fluctuations. With the proposed circuit, a SAR ADC exhibits 83.11 dB of Signal to Noise Ratio at 1.28 MS/s and \(375\,\upmu\hbox {W}\) of power consumption. The PT variations for critical corners are less than 0.58 bits.