文摘
A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18?μm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5?% frequency uncertainty. The whole circuit consumes 5.2?mA under a 1.8?V supply and occupies a die area of 0.55?mm2. Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.