Computationally Efficient Architecture for Accurate Frequency Estimation with Fourier Interpolation

详细信息    查看全文

• 作者：Dongpei Liu (1)
  Hengzhu Liu (1)
  Li Zhou (1)
  Jianfeng Zhang (1)
  Botao Zhang (1)
  
• 关键词：Frequency estimation ; Fast Fourier transformation (FFT) ; Fourier interpolation ; Triple ; mode CORDIC ; Radix ; 4 architecture
• 刊名：Circuits, Systems, and Signal Processing
• 出版年：2014
• 出版时间：March 2014
• 年：2014
• 卷：33
• 期：3
• 页码：781-797
• 全文大小：885 KB
• 参考文献：1. E. Aboutanios, B. Mulgrew, Iterative frequency estimation by interpolation on Fourier coefficients. IEEE Trans. Signal Process. 53(4), 1237-242 (2005) CrossRef
  2. A. Banerjee, A.S. Dhar, Pipelined VLSI architecture using CORDIC for transform domain equalizer. J. Signal Process. Syst. 70, 39-8 (2013) CrossRef
  3. C. Candan, A method for fine resolution frequency estimation from three DFT samples. IEEE Signal Process. Lett.. 18(6), 351-54 (2011) CrossRef
  4. H. Fu, P.Y. Kam, MAP/ML estimation of the frequency and phase of single sinusoid in noise. IEEE Trans. Signal Process. 55(3), 834-45 (2007) CrossRef
  5. W. Hussain, F. Garzia, Designing fast Fourier transform accelerators for orthogonal frequency-division multiplexing systems. J. Signal Process. Syst. 69, 161-71 (2012) CrossRef
  6. E. Jacobsen, P. Kootsookos, Fast, accurate frequency estimator. IEEE Signal Process. Mag. 24(3), 123-25 (2007) CrossRef
  7. Y. Liu, Z. Nie, Z. Zhao, An iterative frequency estimation algorithm using generalized Fourier interpolation. Chin. J. Electron. 18(3), 564-68 (2009)
  8. Y. Liu, Z. Nie, Z. Zhao, Q.H. Liu, Generalization of iterative Fourier interpolation algorithms for single frequency estimation. Digit. Signal Process. 21, 141-49 (2011) CrossRef
  9. D. Liu, H. Liu, J. Zhang, B. Zhang, L. Zhou, VLSI design of a hardware efficient FFT processor, in / Proceeding of Future Information Technology, Application, and Service (2012), pp. 61-0 CrossRef
  10. U. Mengali, A.N. Andrea, / Synchronization Techniques for Digital Receivers (Plenum Press, New York, 1997) CrossRef
  11. G. Michael, R. Burghard, C. Reiner, / Memory Architecture and Parallel Access (Elsevier, New York, 1994)
  12. P.K. Meher, J. Valls, T.B. Juang, K. Sridharan, K. Maharatna, 50 Years of CORDIC: algorithm, architectures and applications. IEEE Trans. Circuits Syst. I, Regul. Pap. 56(9), 1893-907 (2009) CrossRef
  13. P.K. Meher, S.Y. Park, CORDIC designs for fixed angle of rotation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(2), 217-28 (2013) CrossRef
  14. T.O. Pitkanen, J. Takala, Low-power application-specific processor for FFT computations. J. Signal Process. Syst. 63, 165-76 (2011) CrossRef
  15. S.Y. Park, Y.J. Yu, Fixed-point analysis and parameter selections of MSR-CORDIC with applications to FFT designs. IEEE Trans. Signal Process. 60(2), 6245-255 (2012) CrossRef
  16. B.G. Quinn, Estimating frequency by interpolation using Fourier coefficients. IEEE Trans. Signal Process. 42(2), 1264-268 (1994) CrossRef
  17. D.C. Rife, R.R. Boorstyn, Single-tone parameter estimation from discrete-time observation. IEEE Trans. Inf. Theory IT-20(5), 591-98 (1974) CrossRef
  18. T.Y. Sung, H.C. Hsin, Y.P. Cheng, Low-power and high-speed CORDIC-based split-radix FFT processor for OFDM systems. Digit. Signal Process. 20(2), 511-27 (2010) CrossRef
  19. J.H. Takalala, T.S. Jarvinen, H.T. Sorokin, Conflict-free parallel memory access scheme for FFT processors, in / Proceeding of IEEE International Symposium on Circuits and Systems (2003), pp. 524-27
  20. L. Vachhani, K. Sridharan, P.K. Meher, Efficient CORDIC algorithm and architectures for low area and high throughput implementation. IEEE Trans. Circuits Syst. II, Express Briefs 21(2), 61-5 (2009) CrossRef
  21. J.E. Volder, The CORDIC trigonometric computing technique. IRE Trans. Electron. Comput. 20, 330-34 (1959) CrossRef
  22. J.S. Walther, A unified algorithm for elementary function, in / Proceeding of Joint Spring Computer Conference (1971), pp. 379-85
  23. D. Wang, P. Ren, L. Liu, A high-throughput fixed-point complex divider for FPGAs. IEICE Electron. Express 10(4), 1- (2013) CrossRef
  24. H. Xiao, A. Pan, Y. Chan, X. Zeng, Low-cost reconfigurable VLSI architecture for fast Fourier transform. IEEE Trans. Consum. Electron. 54(4), 1617-622 (2008) CrossRef
  
• 作者单位：Dongpei Liu (1)
  Hengzhu Liu (1)
  Li Zhou (1)
  Jianfeng Zhang (1)
  Botao Zhang (1)
  
  1. College of Computer, National University of Defense Technology, Changsha, 410073, China
  
• ISSN：1531-5878

文摘

A simplified DFT-based algorithm and its VLSI implementation for accurate frequency estimation of single-tone complex sinusoid signal are investigated. The proposed algorithm estimates frequency by interpolation using Fourier coefficients. It consists of a coarse search followed by a fine search, and its performance closely achieves the Cramer–Rao low bound (CRLB) even in low SNR region. Moreover, a pipelined triple-mode CORDIC architecture is designed to efficiently support complex multiplication, complex magnitude calculation and real division. The triple-mode CORDIC-based radix-4 architecture is employed for the hardware implementation of the frequency estimator, and is suitable for not only fast Fourier transformation but also accurate frequency estimation. A frequency estimator with 1024-point samples is implemented and verified on FPGA. It works at 215 MHz on a Xilinx XC6VLX240T FPGA device, and uses up 4,161 registers and 6,986 slice LUTs. ASIC synthesis results show that it requires an area of 60K equivalent NAND2 gates with a clock rate of 500 MHz at SMIC 0.18 μm technology. The whole latency of the frequency estimator is 2336 cycles. The proposed architecture provides a good trade off between hardware overhead, estimation performance and computation latency.