VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications

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• 作者：Yu-Hsuan Lee (1)
  Cheng-Wei Pan (1)
  
  1. 135 Yuan-Tung Road ; Chung-Li ; 32003 ; Taoyuan ; Taiwan ; Republic of China
  
• 关键词：DSRC ; VLSI ; FM0 and Manchester
• 刊名：The Journal of VLSI Signal Processing
• 出版年：2015
• 出版时间：February 2015
• 年：2015
• 卷：78
• 期：2
• 页码：199-208
• 全文大小：927 KB
• 参考文献：1. Vehicle Safety Communications鈥擜pplications (VSC-A) Final Report, U.S. Department transactions, national highway traffic safety 532 administration, report DOT HS 811 492A.
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• 刊物类别：Engineering
• 刊物主题：Electrical Engineering
  Circuits and Systems
  Computer Imaging, Vision, Pattern Recognition and Graphics
  Computer Systems Organization and Communication Networks
  Signal,Image and Speech Processing
  Mathematics of Computing
  
• 出版者：Springer New York
• ISSN：1939-8115

文摘

The Dedicated Short-Range Communication (DSRC) is an emerging standard to push the vehicular communication into modern automotive industry. The DSRC standard generally applies FM0 and Manchester to reach DC-balance enhancing the signal reliability. However, the intrinsic unbalance computation load between FM0 and Manchester makes their VLSI architecture with poor hardware utilization. In this paper, the reuse-oriented Boolean simplification (ROBS) technique is proposed to overcome this problem. The ROBS technique constructs the balance-type architecture to improve the hardware utilization rate (HUR) from 50 % to 90 %. The analysis of how the clock-skew affects the balance-type architecture is also discussed. This work is realized by 0.18um 1P6M CMOS technology with cell-based design flow. The gate count is 25.61, which is normalized to a 2-input NAND gate. The power consumption is 6.58uW@27MHz for FM0 encoding and 6.85uW@27MHz for Manchester encoding. The encoding capability is up to 27 Mbps that can fully support the DSRC standards of America, Europe and Japan.