Built-in Self Test Power and Test Time Analysis in On-chip Networks

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• 作者：Mahdieh Nadi Senejani (1)
  Mahdiar Ghadiry (2)
  Chia Yee Ooi (1)
  Muhammad Nadzir Marsono (1)
  
  1. Faculty of Electrical Engineering ; Universiti Teknologi Malaysia ; 81310 ; Johor Bahru ; Johor ; Malaysia
  2. Department of Computer Engineering ; Islamic Azad University ; Arak Branch ; Arak ; Iran
  
• 关键词：On ; chip networks ; Test ; JTAG ; Energy ; Analytical model ; Built ; in self test
• 刊名：Circuits, Systems, and Signal Processing
• 出版年：2015
• 出版时间：April 2015
• 年：2015
• 卷：34
• 期：4
• 页码：1057-1075
• 全文大小：1,303 KB
• 参考文献：1. 1149.1-1990 - IEEE standard test access port and boundary-scan architecture
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  6. M. Ghadiry, M. Nadi, M.T. Manzuri-Shalmani, D. Rahmati, Effect of number of faults on NOC power and performance, in / Proceedings of the 13th International Conference on Parallel and Distributed Systems, ICPADS鈥?7, vol. 1 (2007), pp. 1鈥?
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  12. Nadi, M, Ghadiry, M, Ooi, CY, Marsono, MN (2013) A semi-analytical approach to study the energy consumption of on-chip networks testing. J. Low Power Electron. 9: pp. 189-197 CrossRef
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• 刊物类别：Engineering
• 刊物主题：Electronic and Computer Engineering
  
• 出版者：Birkh盲user Boston
• ISSN：1531-5878

文摘

Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of verification, HSPICE simulation and FPGA implementation are used. The switching activities are computed using a special purpose cycle-accurate NoC simulator. At the end, the model is used to calculate test power and spot the most energy consuming and area occupying component of a typical NoC testing circuit.