Analytical Modeling for Multi-transaction Bus on Distributed Systems

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• 作者：Jih-Ching Chiu (22)
  Kai-Ming Yang (22)
  Chen-Ang Wong (22)
  
• 关键词：On ; Chip Interconnect ; Analytical Performance evaluation
• 刊名：Lecture Notes in Computer Science
• 出版年：2012
• 出版时间：2012
• 年：2012
• 卷：7440
• 期：1
• 页码：10-20
• 全文大小：240KB
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• 作者单位：Jih-Ching Chiu (22)
  Kai-Ming Yang (22)
  Chen-Ang Wong (22)
  
  22. Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan, R.O.C.
  

文摘

Network-on-Chip (NoC) has been proposed to perform high performance and scalability in System-on-Chip (SoC) design. Interconnection modeling was widely used to evaluate performance, especially for large-scale NoCs. In this paper, the router modeling for multi-transaction bus architecture on distributed system with bufferless microarchitectures was presented to analyze and evaluate the performance and model the success rate of each node respectively. It will facilitate the analysis of impact for different priorities. The accuracy of our approach and its practical use is illustrated through extensive simulation results.