InGaZnO TFT behavioral model for IC design
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- 作者：Pydi Bahubalindrun ; Vítor Tavares…
- 关键词：Equivalent circuit approach ; neural models ; Verilog ; A ; a ; IGZO TFT modeling ; a ; IGZO TFT circuits
- 刊名：Analog Integrated Circuits and Signal Processing
- 出版年：2016
- 出版时间：April 2016
- 年：2016
- 卷：87
- 期：1
- 页码：73-80
- 全文大小：983 KB
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Vítor Tavares (2)
Pedro Barquinha (1)
Pedro Guedes de Oliveira (2)
Rodrigo Martins (1)
Elvira Fortunato (1)
1. CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa and CEMOP-UNINOVA, 2829-516, Caparica, Portugal
2. INESC TEC and Faculty of Engineering, University of Porto, Campus FEUP, Rua Dr. Roberto Frias, 378, 4200-465, Porto, Portugal - 刊物类别：Engineering
- 刊物主题：Circuits and Systems
Electronic and Computer Engineering
Signal,Image and Speech Processing - 出版者：Springer Netherlands
- ISSN：1573-1979
文摘
This paper presents a behavioral model for amorphous indium–gallium–zinc oxide thin-film transistor using artificial neural network (ANN) based equivalent circuit (EC) approach to predict static and dynamic behavior of the device. In addition, TFT parasitic capacitances (CGS and CGD) characterization through measurements is also reported. In the proposed model, an EC is derived from the device structure, in terms of electrical lumped elements. Each electrical element in the EC is modeled with an ANN. Then these ANNs are connected together as per the EC and implemented in Verilog-A. The proposed model performance is validated by comparing the circuit simulation results with the measured response of a simple common-source amplifier, which has shown 12.2 dB gain, 50 μW power consumption and 85 kHz 3-dB frequency with a power supply of 6 V. The same circuit is tested as an inverter and its response is also presented up to 50 kHz, from both simulations and measurements. These results show that the model is capable of capturing both small and large signal behavior of the device to good accuracy, even including the harmonic distortion of the signal (that emphasizes the nonlinear behavior of the parasitic capacitance), making the model suitable for IC design.