Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

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• 作者：Najam Muhammad Amin ; Zhi-gong Wang ; Zhi-qun Li
• 关键词：Folded mixer ; Current reuse ; Low power ; Inductorless design ; Direct conversion ; TN4
• 刊名：Frontiers of Information Technology & Electronic Engineering
• 出版年：2014
• 出版时间：December 2014
• 年：2014
• 卷：15
• 期：12
• 页码：1190-1199
• 全文大小：597 KB
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• 作者单位：Najam Muhammad Amin (1)
  Zhi-gong Wang (1)
  Zhi-qun Li (1)
  
  1. Institute of RF- & OE-ICs, Southeast University, Nanjing, 210096, China
  
• 刊物类别：Computer Science, general; Electrical Engineering; Computer Hardware; Computer Systems Organization
• 刊物主题：Computer Science, general; Electrical Engineering; Computer Hardware; Computer Systems Organization and Communication Networks; Electronics and Microelectronics, Instrumentation; Communications Engine
• 出版者：Zhejiang University Press
• ISSN：2095-9230

文摘

We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator (LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency (IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power (LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain (VCG) of 9.8 dB, a double sideband noise figure (DSB-NF) of 11.6 dB, and a linearity in terms of input 1 dB compression point (P _in,1dB) of ?3 dBm are measured. The mixer draws a current of 5 mA from a 1.2 V supply dissipating a power of only 6 mW. Key words Folded mixer Current reuse Low power Inductorless design Direct conversion